All Combinational Circuits Verilog codes through Dataflow modelling

//*****************************
//This post contains all basic combinational circuits verilog code
//using dataflow modelling.
// MUX, DEMUX, Encoder, Decoder, Half Adder, Full Adder, Subtractor,
// Parity Checker and 1 bit comparator
//********************************


module halfadderdf(a,b,s,c);
input a,b;
output s,c;
wire s,c;
assign s=a^b;
assign c=a&b;
endmodule

module fulladderdf(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s,cout;
assign s = a^b^cin;
assign cout = ((a^b)&cin)|(a&b);
endmodule


module mux41df(i,s0,s1,y);
input [3:0]i;
input s0,s1;
output y;
wire y;
assign y= ((i[0] & ~s1 & ~s0)|(i[1] & ~s1 & s0)|(i[2] & s1 & ~s0)|(i[3] & s1 & s0));
endmodule

module demux14df(i,s1,s0,y);
input i,s1,s0;
output [3:0]y;
assign y[0]=(i & ~s1 & ~s0);
assign y[1]=(i & ~s1 & s0);
assign y[2]=(i & s1 & ~s0);
assign y[3]=(i & s1 & s0);
endmodule


module halfsubdf(a,b,diff,bor);
input a,b;
output diff,bor;
assign diff=a^b;
assign bor=~a&b;
endmodule


module fullsubdf(a,b,c,diff,bor);
input a,b,c;
output diff,bor;
assign diff=a^b^c;
assign bor=((a~^b)&c)|(~a&b);
endmodule



module encoder42df(d,y);
output[1:0]y;
input [3:0]d;
assign y[0]= d[1] | d[3];
assign y[1] = d[2] | d[3];
endmodule



module decoder24df(s1,s0,d);
input s1,s0;
output [3:0]d;
assign d[0]= ~s1 & ~s0;
assign d[1]= ~s1 & s0;
assign d[2]= s1 & ~s0;
assign d[3]= s1 & s0;
endmodule



module comparator1bitdf (a,b,l,e,g);
input a,b;
output l,e,g;
assign e = a ~^ b;
assign l = ~a & b;
assign g =  a & ~b;
endmodule



module paritycheckerdf(a,b,c,d,p);
input a,b,c,d;
output p;
assign p = a ^ b ^ c ^ d;
endmodule

1 bit Odd Parity Checker

// BlueTechspot.blogspot.com
module paritychecker(a,b,c,d,p);
input a,b,c,d;
output p;
xor (p,a,b,c,d);
endmodule

One bit comparator Verilog Code

//BlueTechspot.blogspot.com
module comp1b(a,b,e,g,l);
input a,b;
output e,g,l;
xnor(e,a,b);
and(g,a,~b);
and(l,~a,b);
endmodule

4 x 2 Encoder Verilog Code

//BlueTechspot.blogspot.com
module encoder42(d,y);
input [3:0]d;
output [1:0]y;
or(y[0],d[1],d[3]);
or(y[1],d[2],d[3]);
endmodule

2 x 4 Decoder Verilog Code

//BlueTechspot.blogspot.com
module decoder24(x,y,f);
input x,y;
output [3:0]f;
and(f[0],~x,~y);
and(f[1],~x,y);
and(f[2],x,~y);
and(f[3],x,y);
endmodule

1 x 4 DEMUX Verilog Code

//BlueTechspot.blogspot.com
module demux14(i,y,s);
input i;
input [1:0] s;
output [3:0] y;
wire [3:0] y;
and (y[0],~s[0],~s[1],i);
and (y[1],s[0],~s[1],i);
and (y[2],~s[0],s[1],i);
and (y[3],s[0],s[1],i);
endmodule

4 x 1 MUX using 2 x 1 MUX Verilog Code

//BlueTechspot.blogspot.com
module mux21(a,b,s,w);
input a,b,s;
output w;
wire w;
and (w1,a,~s);
and (w2,b,s);
or(w,w1,w2);
endmodule

module mux41(A,S,W);
input [3:0] A;
input [1:0] S;
output W;
wire w1,w2;
mux21 m1 (.a(A[0]),.b(A[1]),.s(S[0]),.w(w1));
mux21 m2 (.a(A[2]),.b(A[3]),.s(S[0]),.w(w2));
mux21 m3 (.a(w1),.b(w2),.s(S[1]),.w(W));
endmodule

Full Subtractor Verilog Code

//BlueTechspot.blogspot.com
module fullsub(a,b,bi,d,bo);
input a,b,bi;
output d,bo;
wire d,bo,w1,w2,w3;
xor (d,a,b,bi);
and(w1,~a,b);
and(w2,b,bi);
and(w3,~a,bi);
or (bo,w1,w2,w3);
endmodule

Half Subtractor Verilog Code

//BlueTechspot.blogspot.com
module halfsub(a,b,d,br);
input a,b;
output br,d;
wire b,d;
xor (d,a,b);
and (br,~a,b);
endmodule

Full Adder using module instantiation

//BlueTechspot.blogspot.com

module halfadder2 (a,b,s,c);

output s,c;

input a,b;

wire s,c;

xor (s,a,b);

and(c,a,b);

endmodule

module fulladder(A,B,Cin,Sum,Cout);

output Sum,Cout;

input A,B,Cin;

wire Sum,Cout,w1,w2,w3;

halfadder2 h1(.a(A),.b(B),.s(w1),.c(w2));

halfadder2 h2(.a(Cin),.b(w1),.s(Sum),.c(w3));

or (Cout,w2,w3);

endmodule

Half Adder Verilog Code

// Blue Techspot - bluetechspot.blogspot.com
module halfadder2 (a,b,s,c);
output s,c;
input a,b;
wire s,c;
xor (s,a,b);
and(c,a,b);
endmodule