1 x 4 DEMUX Verilog Code

//BlueTechspot.blogspot.com
module demux14(i,y,s);
input i;
input [1:0] s;
output [3:0] y;
wire [3:0] y;
and (y[0],~s[0],~s[1],i);
and (y[1],s[0],~s[1],i);
and (y[2],~s[0],s[1],i);
and (y[3],s[0],s[1],i);
endmodule