4 x 1 MUX using 2 x 1 MUX Verilog Code

//BlueTechspot.blogspot.com
module mux21(a,b,s,w);
input a,b,s;
output w;
wire w;
and (w1,a,~s);
and (w2,b,s);
or(w,w1,w2);
endmodule

module mux41(A,S,W);
input [3:0] A;
input [1:0] S;
output W;
wire w1,w2;
mux21 m1 (.a(A[0]),.b(A[1]),.s(S[0]),.w(w1));
mux21 m2 (.a(A[2]),.b(A[3]),.s(S[0]),.w(w2));
mux21 m3 (.a(w1),.b(w2),.s(S[1]),.w(W));
endmodule