2 x 4 Decoder Verilog Code

//BlueTechspot.blogspot.com
module decoder24(x,y,f);
input x,y;
output [3:0]f;
and(f[0],~x,~y);
and(f[1],~x,y);
and(f[2],x,~y);
and(f[3],x,y);
endmodule