02 October, 2018

4 x 2 Encoder Verilog Code

//BlueTechspot.blogspot.com
module encoder42(d,y);
input [3:0]d;
output [1:0]y;
or(y[0],d[1],d[3]);
or(y[1],d[2],d[3]);
endmodule

2 x 4 Decoder Verilog Code

//BlueTechspot.blogspot.com
module decoder24(x,y,f);
input x,y;
output [3:0]f;
and(f[0],~x,~y);
and(f[1],~x,y);
and(f[2],x,~y);
and(f[3],x,y);
endmodule

1 x 4 DEMUX Verilog Code

//BlueTechspot.blogspot.com
module demux14(i,y,s);
input i;
input [1:0] s;
output [3:0] y;
wire [3:0] y;
and (y[0],~s[0],~s[1],i);
and (y[1],s[0],~s[1],i);
and (y[2],~s[0],s[1],i);
and (y[3],s[0],s[1],i);
endmodule