All Combinational Circuits Verilog codes through Dataflow modelling

//*****************************
//This post contains all basic combinational circuits verilog code
//using dataflow modelling.
// MUX, DEMUX, Encoder, Decoder, Half Adder, Full Adder, Subtractor,
// Parity Checker and 1 bit comparator
//********************************


module halfadderdf(a,b,s,c);
input a,b;
output s,c;
wire s,c;
assign s=a^b;
assign c=a&b;
endmodule

module fulladderdf(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s,cout;
assign s = a^b^cin;
assign cout = ((a^b)&cin)|(a&b);
endmodule


module mux41df(i,s0,s1,y);
input [3:0]i;
input s0,s1;
output y;
wire y;
assign y= ((i[0] & ~s1 & ~s0)|(i[1] & ~s1 & s0)|(i[2] & s1 & ~s0)|(i[3] & s1 & s0));
endmodule

module demux14df(i,s1,s0,y);
input i,s1,s0;
output [3:0]y;
assign y[0]=(i & ~s1 & ~s0);
assign y[1]=(i & ~s1 & s0);
assign y[2]=(i & s1 & ~s0);
assign y[3]=(i & s1 & s0);
endmodule


module halfsubdf(a,b,diff,bor);
input a,b;
output diff,bor;
assign diff=a^b;
assign bor=~a&b;
endmodule


module fullsubdf(a,b,c,diff,bor);
input a,b,c;
output diff,bor;
assign diff=a^b^c;
assign bor=((a~^b)&c)|(~a&b);
endmodule



module encoder42df(d,y);
output[1:0]y;
input [3:0]d;
assign y[0]= d[1] | d[3];
assign y[1] = d[2] | d[3];
endmodule



module decoder24df(s1,s0,d);
input s1,s0;
output [3:0]d;
assign d[0]= ~s1 & ~s0;
assign d[1]= ~s1 & s0;
assign d[2]= s1 & ~s0;
assign d[3]= s1 & s0;
endmodule



module comparator1bitdf (a,b,l,e,g);
input a,b;
output l,e,g;
assign e = a ~^ b;
assign l = ~a & b;
assign g =  a & ~b;
endmodule



module paritycheckerdf(a,b,c,d,p);
input a,b,c,d;
output p;
assign p = a ^ b ^ c ^ d;
endmodule

1 bit Odd Parity Checker

// BlueTechspot.blogspot.com
module paritychecker(a,b,c,d,p);
input a,b,c,d;
output p;
xor (p,a,b,c,d);
endmodule

One bit comparator Verilog Code

//BlueTechspot.blogspot.com
module comp1b(a,b,e,g,l);
input a,b;
output e,g,l;
xnor(e,a,b);
and(g,a,~b);
and(l,~a,b);
endmodule