Full Subtractor Verilog Code

//BlueTechspot.blogspot.com
module fullsub(a,b,bi,d,bo);
input a,b,bi;
output d,bo;
wire d,bo,w1,w2,w3;
xor (d,a,b,bi);
and(w1,~a,b);
and(w2,b,bi);
and(w3,~a,bi);
or (bo,w1,w2,w3);
endmodule